
6
5
4
3
2
1
REVISION RECORD
LTR
ECO NO:
APPROVED:
DATE:
D
PF4/PPI_D4/TFS0/TACLK0
PF6/PPI_D6/DT0SEC/TACI0
PF10/PPI_D10/RFS1/SPISEL7
PF12/PPI_D12/DT1PRI/SPISEL2/COG
PF14/PPI_D14/DT1SEC/UART1TX
PF5/PPI_D5/TSCLK0/TACLK1
PF7/PPI_D7/DR0SEC/TACI1
PF9/PPI_D9/RSCLK1/SPISEL6
PF11/PPI_D11/TFS1/CZM
PF13/PPI_D13/TSCLK1/SPISEL3/CUD
PF15/PPI_D15/DR1SEC/UART1RX/TACI3
D
Will be driven low as soon
as core is ready to boot.
C
PG6/DT0PRIA/TMR2/PPI_FS3
PG8/TMR4/RFS0A/UART0RX/TACI4
PG10/TMR6/TSCLK0A/TACI6
PG14/TSCLK0A1/MOC
PG7/TMR3/DR0PRIA/UART0TX
PG9/TMR5/RSCLK0A/TACI5
PG13/UART1RXA/TACI2
PG15/TFS0A/MII_PHYINT/RMII_MDINT
JTAG
C
Remove Pin 3 for keying
PH4/MII_TXCLK/RMII_REFCLK
PH8/SPISEL4/ERXD1/TACLK2
PH9/SPISEL5/ETXD2/TACLK3
B
B
ANALOG DEVICES
SYSTEM DEMONSTRATION PLATFORM
A
DRAWN:
CHECKED:
QUALITY CONTROL:
DATED:
13-01-09
DATED:
14-01-10
DATED:
COMPANY:
TITLE:
CODE: SIZE: DRAWING NO: REV:
(BLACKFIN I/O)
SDP1Z B
A
RELEASED:
DATED:
SCALE:
SHEET: 4 OF 6